1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly to a plasma display apparatus capable of generating stable discharge under the conditions of high resolution and high temperature to realize a screen and a method of driving the same.
2. Description of the Background Art
In general, a plasma display panel (PDP) emits light from a fluorescent body by ultraviolet (UV) rays of 147 nm generated when an inactive mixed gas such as He+Xe or Ne+Xe is discharged to display images including characters and graphics.
FIG. 1 is a perspective view illustrating the structure of a conventional three-electrode AC surface discharge type PDP having discharge cells arranged in a matrix. Referring to FIG. 1, a three-electrode AC surface discharge type PDP 100 includes a scan electrode 11a and a sustain electrode 12a formed on a top substrate 10 and an address electrode 22 formed on a bottom substrate 20. The scan electrode 11a and the sustain electrode 12a are formed of a transparent electrode, for example, indium-tin-oxide (ITO), respectively. Metal bus electrodes 11b and 12b for reducing resistance are formed in the scan electrode 11a and the sustain electrode 12a, respectively. A top dielectric layer 13a and a protective layer 14 are laminated on the top substrate 10 on which the scan electrode 11a and the sustain electrode 12a are formed. Wall charges generated during plasma discharge are accumulated on the top dielectric layer 13a. The protective layer 14 prevents the top dielectric layer 13a from being damaged by sputtering generated during plasma discharge and improves efficiency of emitting secondary electrons. MgO is commonly used as the protective layer 14.
On the other hand, a bottom dielectric layer 13b and a partition wall 21 are formed on a bottom substrate 20 on which the address electrode 22 is formed and the surfaces of the bottom dielectric layer 13b and the partition wall 21 are coated with a fluorescent body layer 23. The address electrode 22 is formed to intersect the scan electrode 11a and the sustain electrode 12a. The partition wall 21 is formed to run parallel with the address electrode 22 to prevent ultraviolet (UV) rays and visible rays generated by discharge from leaking to an adjacent discharge cell. The fluorescent body layer 23 is excited by the UV rays generated during plasma discharge to generate any one visible ray among red (R), green (G), and blue (B) visible rays. An inactive mixed gas such as He+Xe or Ne+Xe for discharge is implanted into a discharge space of discharge cells partitioned by the partition wall 21 provided between the top substrate 10 and the bottom substrate 20. A method of driving a conventional PDP having such a structure will be described with reference to FIG. 2.
FIG. 2 illustrates driving waveforms in accordance with the method of driving the conventional PDP. As illustrated in FIG. 2, the waveforms in accordance with the method of driving the conventional PDP are composed of a reset period, an address period, and a sustain period and the reset period is composed of a set-up period and a set-down period.
A ramp up pulse is applied to scan electrodes Y in the set-up period such that positive wall charges are accumulated on the sustain electrodes Z and the address electrodes X and that negative wall charges are accumulated on the scan electrodes Y.
A ramp down pulse is applied in the set-down period such that the wall charges that are excessively accumulated by the high pressure ramp up pulse are uniformly reduced to a certain level.
In the address period, address discharge is generated by the scan pulse of the scan electrodes Y and the data pulse of the address electrodes X and a sustain voltage Vs is maintained in the sustain electrodes Z. At this time, the amount of the bias voltage Vs applied to the sustain electrodes Z is maintained such that the bias voltage Vs does not generate discharge with the scan pulse applied to the scan electrodes Y.
In the sustain period, sustain pulses are alternately applied to the scan electrodes Y and the sustain electrodes Z such that sustain discharge is generated.
FIG. 3 illustrates the state of wall charges in accordance with the driving waveforms of the conventional PDP. FIG. 3(a) illustrates the state of the wall charges formed by the set-up discharge generated by the high pressure ramp up pulse in the set-up period. It is noted that a large amount of wall charges are formed on the scan electrodes Y, the sustain electrodes Z, and the address electrodes X by the high pressure ramp up pulse.
FIG. 3(b) illustrates the state of wall charges formed in accordance with a discharge process by the ramp down pulse in the set-down period. The wall charges that are excessively accumulated by the ramp down pulse are reduced to a certain level such that the wall charges of the respective cells become uniform.
FIG. 3(c) illustrates the state of wall charges immediately after the scan pulse and the data pulse are applied to the scan electrodes Y and the address electrodes X, respectively, in the address period, which is inverse to the state of the wall charges of FIG. 3(b).
FIG. 3(d) illustrates the state of wall charges in the second half of the address period in the cell where address discharge was previously generated in the first half of the address period, in which more wall charges are lost than in FIG. 3(c). The state of the wall charges of the cell, which are generated by the address discharge in the first half of the address period, must be maintained to the second half of the address period. However, when a large amount of wall charges are lost as illustrated in FIG. 3(d), the sustain discharge that follows the address discharge may not be normally performed.
The reason why the state of the wall charges in the cell where the address discharge was previously generated is not maintained to the second half of the address period but the wall charges are lost as illustrated in FIG. 3(d) is as follows.
The higher the resolution of a PDP is, the longer the address period is. Therefore, the wall charges formed by the address discharge of an initial scan line as illustrated in FIG. 3(c) are in the same voltage state of the scan electrodes Y and the sustain electrodes Z to the point of time where the address period is finished as illustrated in FIG. 3(d). Therefore, after the lapse of a large amount of time, charges are naturally combined with each other such that the wall charges are lost.
A scan bias voltage Vsc for generating the scan pulse is applied to the initial scan electrodes Y in which the address period starts. According as the scan bias voltage Vsc becomes higher, the scan bias voltage Vsc holds the negative wall charges formed on the scan electrodes Y before scan is performed.
However, although the positive wall charges are formed on the scan electrodes Y after the address discharge is generated, the scan bias voltage Vsc is maintained in the scan electrodes Y. Therefore, according as the time for which the scan bias voltage Vsc is maintained increases, the positive wall charges formed after the address discharge are lost. Such a phenomenon easily occurs when resolution increases and a plasma display apparatus is operated at a high temperature.